1. Field of the Invention
The present invention relates to apparatus and methods for fabricating microelectronic devices. In particular, the present invention relates to using a stress shield in the fabrication of microelectronic devices to reduce stress at corners and/or edges of microelectronic dice within the microelectronic devices.
2. State of the Art
As the size of electronic devices employing microelectronic dice continues to shrink and as the cost of such devices continues to fall, device manufacturers seek methods to incorporate microelectronic dice into their devices as efficiently as possible. The microelectronic dice should not require a large amount of space to mount, but must be securely and reliably affixed to their carrier substrates. The mounting method employed also should be as simple as possible, minimizing the time and equipment needed to mount the microelectronic dice to the substrates.
One mounting technology is called flip chip or C4 (xe2x80x9cControlled Collapse Chip Connectionxe2x80x9d) attachment, which is an inverted microelectronic die mounted to a substrate with a bumping process. As shown in FIG. 8a, a flip chip 200 is a microelectronic die that has a pattern or array of terminations or bond pads 202, generally metal or metal alloy pads, spaced on an active surface 204 of the flip chip 200. An array of minute solder balls 206, generally lead/tin solder, is disposed on the flip chip bond pads 202, as shown in FIG. 8b. 
The flip chip 200 is then positioned (i.e., flipped) such that the solder balls 206 are aligned with an array of bond pads 216 on an active surface 214 of a carrier substrate 212, as shown in FIG. 8c. The carrier substrate bond pads 216 are essentially in mirror-image placement to the flip chip bond pads 202. It is, of course, understood that the solder balls 206 could be formed on the carrier substrate bond pads 216, rather than the flip chip bond pads 202. The solder balls 206 are then heated thereby reflowing them, such that when cooled the solder balls 206 solidify to form conductive pillars between the flip chip bond pads 202 and the carrier substrate bond pads 216. An underflow material 218 is disposed between the flip chip 200 and the carrier substrate 212 to secure the flip chip 200 and to prevent possible contamination. This attachment technique is also used in C4 OLGA (xe2x80x9cOrganic Land Grid Arrayxe2x80x9d) and FCPGA (xe2x80x9cFlip Chip Pin Grid Arrayxe2x80x9d) packages, as known in the art.
Another technology is called Chip-on-Flex (xe2x80x9cCOFxe2x80x9d) packaging, which is shown in FIGS. 9a-9d. A flex component 232 (i.e., the carrier substrate) is attached with an adhesive layer 230 to an active surface 234 of microelectronic die 236, as shown in FIG. 9a. The microelectronic die active surface 234 includes at least one contact 238. The microelectronic die 236 is then encapsulated with an encapsulating material 242, such as plastics, resins, and the like, as shown in FIG. 9b, that covers a back surface 244 and side(s) 246 of the microelectronic die 236, and abuts a bottom surface 248 of the adhesive layer 230 (the portion not covered by the microelectronic die 236).
As shown in FIG. 9c, a plurality of conductive traces 254 are formed on an upper surface 256 of the flex component 232 and extend into vias 258 (formed through the flex component 232 and adhesive layer 230) to contact the contacts 238. The vias 258 may be formed by any known technique, but are general formed by laser ablation. The conductive traces 254 may also be formed by any known technique, such as photolithography.
As shown in FIG. 9d, a plurality of additional flex component layers are stacked by attaching one atop another, represented by elements 232xe2x80x2 and 232xe2x80x3, with additional conductive traces formed thereon, represented by elements 254xe2x80x2 and 254xe2x80x3. A layer of solder resist 262 is then applied over the uppermost flex component layer and conductive traces, represented by elements 232xe2x80x2 and 254xe2x80x3, respectively. A plurality of vias 264 are formed through the solder resist layer 262 to expose a portion of the uppermost conductive trace, represented as element 254xe2x80x3 and external contacts are formed on the conductive traces 254xe2x80x3 (shown as solder balls 266). The solder balls 266 may be attached to a substrate in a manner similar to flip chip attachment, as shown in FIGS. 8a-8c. 
Although the discussed techniques are widely used in the industry, the devices made from such techniques suffer from stress problems. The stresses are caused by a mismatch in the coefficients of thermal expansion (xe2x80x9cCTExe2x80x9d) between the microelectronic dice and the packaging material (substrates, flex components, dielectric layers, etc.). These CTE induced stresses can cause mechanical damage including, but not limited to thin-film cracking and/or delamination, detachment of solder balls from the microelectronic die or the substrate, and cracking of the microelectronic dice. This problem can be lessened by excluding sensitive circuitry from the corners and/or edges of the microelectronic die. However, this approach is prohibitively expensive.
Therefore, it would be advantageous to develop an apparatus and technique to effectively achieve attachment of a microelectronic die to a supporting substrate, while eliminating or substantially reducing the potential for mechanical damage due to CTE mismatch.